The main objective of the project is to make the scalability, flexibility and speedup of encryption algorithms using FPGA devices. First offloads the process of encryption from the master CPU onto a co-processor, which frees the master CPU resources for other uses. Second, its implementation on FPGA offers the possibility of using many threads to run the Encryption algorithms. Different optimizations have been applied on the hardware architecture of Encryption algorithms , in order to satisfy different constraints in terms of latency, area occupation andspeed. Performance measurement of the hardware solution is compared to AES software implemented on a NIOS II processor. A strong focus is devoted to the achievement of high through- put, which is required to support security requirements for current and future high bandwidth applications.
This project shows that Alteras Cyclone II series FPGA and NIOS II CPU make a low-cost and compact solution that adds high-speed features at lower cost and high degree of flexibility. Various architectures of AES unit was implemented with strong emphasis on high speed performance. FPGA technology has matured to the point where high throughput can be easily obtained.
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